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<a name="RISC_002dV-Options"></a>
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<hr>
<a name="RISC_002dV-Options-1"></a>
<h4 class="subsection">3.19.42 RISC-V Options</h4>
<a name="index-RISC_002dV-Options"></a>

<p>These command-line options are defined for RISC-V targets:
</p>
<dl compact="compact">
<dt><code>-mbranch-cost=<var>n</var></code></dt>
<dd><a name="index-mbranch_002dcost-3"></a>
<p>Set the cost of branches to roughly <var>n</var> instructions.
</p>
</dd>
<dt><code>-mplt</code></dt>
<dt><code>-mno-plt</code></dt>
<dd><a name="index-plt"></a>
<p>When generating PIC code, do or don&rsquo;t allow the use of PLTs. Ignored for
non-PIC.  The default is <samp>-mplt</samp>.
</p>
</dd>
<dt><code>-mabi=<var>ABI-string</var></code></dt>
<dd><a name="index-mabi-3"></a>
<p>Specify integer and floating-point calling convention.  <var>ABI-string</var>
contains two parts: the size of integer types and the registers used for
floating-point types.  For example &lsquo;<samp>-march=rv64ifd -mabi=lp64d</samp>&rsquo; means that
&lsquo;<samp>long</samp>&rsquo; and pointers are 64-bit (implicitly defining &lsquo;<samp>int</samp>&rsquo; to be
32-bit), and that floating-point values up to 64 bits wide are passed in F
registers.  Contrast this with &lsquo;<samp>-march=rv64ifd -mabi=lp64f</samp>&rsquo;, which still
allows the compiler to generate code that uses the F and D extensions but only
allows floating-point values up to 32 bits long to be passed in registers; or
&lsquo;<samp>-march=rv64ifd -mabi=lp64</samp>&rsquo;, in which no floating-point arguments will be
passed in registers.
</p>
<p>The default for this argument is system dependent, users who want a specific
calling convention should specify one explicitly.  The valid calling
conventions are: &lsquo;<samp>ilp32</samp>&rsquo;, &lsquo;<samp>ilp32f</samp>&rsquo;, &lsquo;<samp>ilp32d</samp>&rsquo;, &lsquo;<samp>lp64</samp>&rsquo;,
&lsquo;<samp>lp64f</samp>&rsquo;, and &lsquo;<samp>lp64d</samp>&rsquo;.  Some calling conventions are impossible to
implement on some ISAs: for example, &lsquo;<samp>-march=rv32if -mabi=ilp32d</samp>&rsquo; is
invalid because the ABI requires 64-bit values be passed in F registers, but F
registers are only 32 bits wide.  There is also the &lsquo;<samp>ilp32e</samp>&rsquo; ABI that can
only be used with the &lsquo;<samp>rv32e</samp>&rsquo; architecture.  This ABI is not well
specified at present, and is subject to change.
</p>
</dd>
<dt><code>-mfdiv</code></dt>
<dt><code>-mno-fdiv</code></dt>
<dd><a name="index-mfdiv"></a>
<p>Do or don&rsquo;t use hardware floating-point divide and square root instructions.
This requires the F or D extensions for floating-point registers.  The default
is to use them if the specified architecture has these instructions.
</p>
</dd>
<dt><code>-mdiv</code></dt>
<dt><code>-mno-div</code></dt>
<dd><a name="index-mdiv-4"></a>
<p>Do or don&rsquo;t use hardware instructions for integer division.  This requires the
M extension.  The default is to use them if the specified architecture has
these instructions.
</p>
</dd>
<dt><code>-march=<var>ISA-string</var></code></dt>
<dd><a name="index-march-12"></a>
<p>Generate code for given RISC-V ISA (e.g. &lsquo;<samp>rv64im</samp>&rsquo;).  ISA strings must be
lower-case.  Examples include &lsquo;<samp>rv64i</samp>&rsquo;, &lsquo;<samp>rv32g</samp>&rsquo;, &lsquo;<samp>rv32e</samp>&rsquo;, and
&lsquo;<samp>rv32imaf</samp>&rsquo;.
</p>
</dd>
<dt><code>-mtune=<var>processor-string</var></code></dt>
<dd><a name="index-mtune-11"></a>
<p>Optimize the output for the given processor, specified by microarchitecture
name.  Permissible values for this option are: &lsquo;<samp>rocket</samp>&rsquo;,
&lsquo;<samp>sifive-3-series</samp>&rsquo;, &lsquo;<samp>sifive-5-series</samp>&rsquo;, &lsquo;<samp>sifive-7-series</samp>&rsquo;,
and &lsquo;<samp>size</samp>&rsquo;.
</p>
<p>When <samp>-mtune=</samp> is not specified, the default is &lsquo;<samp>rocket</samp>&rsquo;.
</p>
<p>The &lsquo;<samp>size</samp>&rsquo; choice is not intended for use by end-users.  This is used
when <samp>-Os</samp> is specified.  It overrides the instruction cost info
provided by <samp>-mtune=</samp>, but does not override the pipeline info.  This
helps reduce code size while still giving good performance.
</p>
</dd>
<dt><code>-mpreferred-stack-boundary=<var>num</var></code></dt>
<dd><a name="index-mpreferred_002dstack_002dboundary"></a>
<p>Attempt to keep the stack boundary aligned to a 2 raised to <var>num</var>
byte boundary.  If <samp>-mpreferred-stack-boundary</samp> is not specified,
the default is 4 (16 bytes or 128-bits).
</p>
<p><strong>Warning:</strong> If you use this switch, then you must build all modules with
the same value, including any libraries.  This includes the system libraries
and startup modules.
</p>
</dd>
<dt><code>-msmall-data-limit=<var>n</var></code></dt>
<dd><a name="index-msmall_002ddata_002dlimit"></a>
<p>Put global and static data smaller than <var>n</var> bytes into a special section
(on some targets).
</p>
</dd>
<dt><code>-msave-restore</code></dt>
<dt><code>-mno-save-restore</code></dt>
<dd><a name="index-msave_002drestore"></a>
<p>Do or don&rsquo;t use smaller but slower prologue and epilogue code that uses
library function calls.  The default is to use fast inline prologues and
epilogues.
</p>
</dd>
<dt><code>-mstrict-align</code></dt>
<dt><code>-mno-strict-align</code></dt>
<dd><a name="index-mstrict_002dalign-2"></a>
<p>Do not or do generate unaligned memory accesses.  The default is set depending
on whether the processor we are optimizing for supports fast unaligned access
or not.
</p>
</dd>
<dt><code>-mcmodel=medlow</code></dt>
<dd><a name="index-mcmodel_003dmedlow"></a>
<p>Generate code for the medium-low code model. The program and its statically
defined symbols must lie within a single 2 GiB address range and must lie
between absolute addresses -2 GiB and +2 GiB. Programs can be
statically or dynamically linked. This is the default code model.
</p>
</dd>
<dt><code>-mcmodel=medany</code></dt>
<dd><a name="index-mcmodel_003dmedany"></a>
<p>Generate code for the medium-any code model. The program and its statically
defined symbols must be within any single 2 GiB address range. Programs can be
statically or dynamically linked.
</p>
</dd>
<dt><code>-mexplicit-relocs</code></dt>
<dt><code>-mno-exlicit-relocs</code></dt>
<dd><p>Use or do not use assembler relocation operators when dealing with symbolic
addresses.  The alternative is to use assembler macros instead, which may
limit optimization.
</p>
</dd>
<dt><code>-mrelax</code></dt>
<dt><code>-mno-relax</code></dt>
<dd><p>Take advantage of linker relaxations to reduce the number of instructions
required to materialize symbol addresses. The default is to take advantage of
linker relaxations.
</p>
</dd>
<dt><code>-memit-attribute</code></dt>
<dt><code>-mno-emit-attribute</code></dt>
<dd><p>Emit (do not emit) RISC-V attribute to record extra information into ELF
objects.  This feature requires at least binutils 2.32.
</p>
</dd>
<dt><code>-malign-data=<var>type</var></code></dt>
<dd><a name="index-malign_002ddata"></a>
<p>Control how GCC aligns variables and constants of array, structure, or union
types.  Supported values for <var>type</var> are &lsquo;<samp>xlen</samp>&rsquo; which uses x register
width as the alignment value, and &lsquo;<samp>natural</samp>&rsquo; which uses natural alignment.
&lsquo;<samp>xlen</samp>&rsquo; is the default.
</p></dd>
</dl>

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